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» Predicting Lattice Reduction
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139
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ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
15 years 7 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
IEEEMM
2007
146views more  IEEEMM 2007»
15 years 3 months ago
Learning Microarray Gene Expression Data by Hybrid Discriminant Analysis
— Microarray technology offers a high throughput means to study expression networks and gene regulatory networks in cells. The intrinsic nature of high dimensionality and small s...
Yijuan Lu, Qi Tian, Maribel Sanchez, Jennifer L. N...
120
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CORR
2010
Springer
163views Education» more  CORR 2010»
15 years 2 months ago
Faster Rates for training Max-Margin Markov Networks
Structured output prediction is an important machine learning problem both in theory and practice, and the max-margin Markov network (M3 N) is an effective approach. All state-of-...
Xinhua Zhang, Ankan Saha, S. V. N. Vishwanathan
133
Voted
CVPR
2005
IEEE
16 years 6 months ago
Multi-Output Regularized Projection
Dimensionality reduction via feature projection has been widely used in pattern recognition and machine learning. It is often beneficial to derive the projections not only based o...
Kai Yu, Shipeng Yu, Volker Tresp
GLVLSI
2006
IEEE
90views VLSI» more  GLVLSI 2006»
15 years 10 months ago
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
Chang Woo Kang, Massoud Pedram