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124
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FPGA
1998
ACM
125views FPGA» more  FPGA 1998»
15 years 8 months ago
Timing Driven Floorplanning on Programmable Hierarchical Targets
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
S. A. Senouci, A. Amoura, Helena Krupnova, Gabriel...
132
Voted
DAC
1997
ACM
15 years 8 months ago
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach
Novel test bench techniques are required to cope with a functional test complexity which is predicted to grow much more strongly than design complexity. Our test bench approach at...
Matthias Bauer, Wolfgang Ecker
SIGGRAPH
1996
ACM
15 years 8 months ago
Consequences of Stratified Sampling in Graphics
Antialiased pixel values are often computed as the mean of N point samples. Using uniformly distributed random samples, the central limit theorem predicts a variance of the mean o...
Don P. Mitchell
106
Voted
AAAI
2008
15 years 6 months ago
AnalogySpace: Reducing the Dimensionality of Common Sense Knowledge
We are interested in the problem of reasoning over very large common sense knowledge bases. When such a knowledge base contains noisy and subjective data, it is important to have ...
Robert Speer, Catherine Havasi, Henry Lieberman
DSN
2008
IEEE
15 years 5 months ago
An accurate flip-flop selection technique for reducing logic SER
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja