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» Predicting Lattice Reduction
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135
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IPPS
2003
IEEE
15 years 9 months ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
138
Voted
RTSS
2003
IEEE
15 years 9 months ago
Experimental Evaluation of Code Properties for WCET Analysis
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
Antoine Colin, Stefan M. Petters
GECCO
2010
Springer
162views Optimization» more  GECCO 2010»
15 years 8 months ago
Heuristics for sampling repetitions in noisy landscapes with fitness caching
For many large-scale combinatorial search/optimization problems, meta-heuristic algorithms face noisy objective functions, coupled with computationally expensive evaluation times....
Forrest Stonedahl, Susa H. Stonedahl
ICPP
1999
IEEE
15 years 8 months ago
Producer-Push - A Protocol Enhancement to Page-Based Software Distributed Shared Memory Systems
This paper describes a technique called producer-push that enhances the performance of a page-based software distributed shared memory system. Shared data, in software DSM systems...
Sven Karlsson, Mats Brorsson
ITC
1999
IEEE
105views Hardware» more  ITC 1999»
15 years 8 months ago
Finite state machine synthesis with concurrent error detection
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...