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PLDI
2003
ACM
14 years 29 days ago
Taming the IXP network processor
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
Lal George, Matthias Blume
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
14 years 2 months ago
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizin...
Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian...
ISVLSI
2008
IEEE
117views VLSI» more  ISVLSI 2008»
14 years 2 months ago
In Situ Design of Register Operations
We present methods to design programs or electronic circuits, for performing any operation on k registers of any sizes in a processor, in such a way that one uses no other working...
Serge Burckel, Emeric Gioan
POPL
2003
ACM
14 years 8 months ago
Bitwidth aware global register allocation
Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is assigned a r...
Sriraman Tallam, Rajiv Gupta
FPGA
1995
ACM
120views FPGA» more  FPGA 1995»
13 years 11 months ago
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses
A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapat...
Baher Haroun, Behzad Sajjadi