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» Procedural Modeling of Interconnected Structures
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IOLTS
2003
IEEE
133views Hardware» more  IOLTS 2003»
14 years 2 months ago
Power Consumption of Fault Tolerant Codes: the Active Elements
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
Daniele Rossi, Steven V. E. S. van Dijk, Richard P...
ICSE
1999
IEEE-ACM
14 years 1 months ago
Using Off-the-Shelf Middleware to Implement Connectors in Distributed Software Architectures
Software architectures promote development focused on modular building blocks and their interconnections. Since architecture-level components often contain complex functionality, ...
Eric M. Dashofy, Nenad Medvidovic, Richard N. Tayl...
CSUR
2006
147views more  CSUR 2006»
13 years 8 months ago
A survey of research and practices of Network-on-chip
resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
Tobias Bjerregaard, Shankar Mahadevan
DSN
2002
IEEE
14 years 1 months ago
Model Checking Performability Properties
Model checking has been introduced as an automated technique to verify whether functional properties, expressed in a formal logic like computational tree logic (CTL), do hold in a...
Boudewijn R. Haverkort, Lucia Cloth, Holger Herman...
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
14 years 11 days ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang