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PDPTA
2000
13 years 9 months ago
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures
The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future ...
Jürgen Becker, Manfred Glesner, Ahmad Alsolai...
DDECS
2009
IEEE
116views Hardware» more  DDECS 2009»
13 years 8 months ago
MTPP - Modular Traffic Processing Platform
High-speed (10 Gb/s and above) network monitoring and traffic processing requires hardware acceleration. Different applications require different functions to be placed in hardware...
Jiri Halak, Sven Ubik
ERSA
2009
131views Hardware» more  ERSA 2009»
13 years 5 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
MAM
2008
150views more  MAM 2008»
13 years 7 months ago
FPGA based string matching for network processing applications
String matching is a key problem in many network processing applications. Current implementations of this process using software are time consuming and cannot meet gigabit bandwid...
Janardhan Singaraju, John A. Chandy
AHS
2007
IEEE
239views Hardware» more  AHS 2007»
13 years 11 months ago
Separation of Data flow and Control flow in Reconfigurable Multi-core SoCs using the Gannet Service-based Architecture
This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...
Wim Vanderbauwhede