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» Process Isolation for Reconfigurable Hardware
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IPPS
2006
IEEE
14 years 1 months ago
Investigation into programmability for layer 2 protocol frame delineation architectures
This paper presents the design and study of reconfigurable architectures for two data-link layer frame delineation techniques used for ATM and GFP. The architectures are targeted ...
Ciaran Toal, Sakir Sezer
TACO
2008
130views more  TACO 2008»
13 years 7 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
LCN
2006
IEEE
14 years 1 months ago
Efficient Packet Processing in User-Level OSes: A Study of UML
Network server consolidation has become popular through recent virtualization technology that builds secure, isolated network systems on shared hardware. One of the virtualization...
Younggyun Koh, Calton Pu, Sapan Bhatia, Charles Co...
DSD
2010
IEEE
141views Hardware» more  DSD 2010»
13 years 5 months ago
Adaptive Beamforming Using the Reconfigurable MONTIUM TP
Until a decade ago, the concept of phased array beamforming was mainly implemented with mechanical or analog solutions. Today, digital hardware has become powerful enough to perfor...
Marcel D. van de Burgwal, Kenneth C. Rovers, Koen ...
JRTIP
2008
249views more  JRTIP 2008»
13 years 7 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...