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» Process Isolation for Reconfigurable Hardware
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ANCS
2010
ACM
13 years 5 months ago
An architecture for software defined cognitive radio
As we move forward towards the next generation of wireless protocols, the push for a better radio physical layer is ever increasing. Conventional radio architectures are limited t...
Aveek Dutta, Dola Saha, Dirk Grunwald, Douglas C. ...
OSDI
2008
ACM
14 years 8 months ago
Block Mason
The flexibility provided by hardware virtualization allows administrators to rapidly create, destroy, and migrate systems across physical hosts. Unfortunately, the storage systems...
Dutch T. Meyer, Brendan Cully, Jake Wires, Norman ...
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
14 years 1 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
IPPS
2005
IEEE
14 years 1 months ago
Stream PRAM
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
Darrell R. Ulm, Michael Scherger
IPPS
2006
IEEE
14 years 1 months ago
Selection of instruction set extensions for an FPGA embedded processor core
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....