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HOTI
2005
IEEE
14 years 2 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
RTAS
1998
IEEE
14 years 1 months ago
Managing Memory Requirements in the Synthesis of Real-Time Systems from Processing Graphs
In the past, environmental restrictions on size, weight, and power consumption have severely limited both the processing and storage capacity of embedded signal processing systems...
Steve Goddard, Kevin Jeffay
CCGRID
2003
IEEE
14 years 13 days ago
Kernel Level Speculative DSM
Interprocess communication (IPC) is ubiquitous in today's computing world. One of the simplest mechanisms for IPC is shared memory. We present a system that enhances the Syst...
Cristian Tapus
IISWC
2008
IEEE
14 years 3 months ago
Temporal streams in commercial server applications
Commercial server applications remain memory bound on modern multiprocessor systems because of their large data footprints, frequent sharing, complex non-strided access patterns, ...
Thomas F. Wenisch, Michael Ferdman, Anastasia Aila...
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
14 years 3 months ago
Adaptive prefetching for shared cache based chip multiprocessors
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
Mahmut T. Kandemir, Yuanrui Zhang, Ozcan Ozturk