This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steve...
Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic de...
Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste...
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
The purpose of our on going research would be to track entities, which enter their field of vision over the sensor network. Based on their sightings, they maintain a dynamic cache ...
Arvind Nath Rapaka, Sandeep Bogollu, Donald C. Wun...
Database processes must be cache-efficient to effectively utilize modern hardware. In this paper, we analyze the importance of temporal locality and the resultant cache behavior ...