6819 search results - page 19 / 1364 » Process Reuse Architecture |
CODES
2000
IEEE
13 years 12 months ago
2000
IEEE
In the design of embedded systems-on-chip, the success of a product generation depends on the exibility to accommodate future design changes. This requirement in uences the hardwa...
COOPIS
2002
IEEE
14 years 14 days ago
2002
IEEE
The design of virtual workplaces that can support virtual work processes has traditionally been either ad-hoc, or has been influenced by the top-down approaches, such as ‘virtua...
ICON
2007
IEEE
14 years 1 months ago
2007
IEEE
This study proposes a novel WDM EPON system based upon an AWG, in which multiple wavelengths are established in both the upstream and the downstream fibers. The use of the AWG devi...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
ICML
1998
IEEE
14 years 8 months ago
1998
IEEE
This paper introduces the RL-TOPs architecture for robot learning, a hybrid system combining teleo-reactive planning and reinforcement learning techniques. The aim of this system ...