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ARC
2010
Springer
167views Hardware» more  ARC 2010»
13 years 10 months ago
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
Kunjan Patel, Chris J. Bleakley
ICSE
2004
IEEE-ACM
14 years 7 months ago
The Dublo Architecture Pattern for Smooth Migration of Business Information Systems: An Experience Report
While the importance of multi-tier architectures for enterprise information systems is widely accepted and their benefits are well published, the systematic migration from monolit...
Wilhelm Hasselbring, Ralf Reussner, Holger Jaekel,...
CASES
2003
ACM
14 years 22 days ago
Vectorizing for a SIMdD DSP architecture
The Single Instruction Multiple Data (SIMD) model for fine-grained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demon...
Dorit Naishlos, Marina Biberstein, Shay Ben-David,...