Sciweavers

51 search results - page 5 / 11
» Process Variation Tolerant 3T1D-Based Cache Architectures
Sort
View
DSN
2002
IEEE
14 years 2 months ago
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...
Jiri Gaisler
ISQED
2007
IEEE
163views Hardware» more  ISQED 2007»
14 years 4 months ago
Variation Analysis of CAM Cells
Process related variations are considered a major concern in emerging sub-65nm technologies. In this paper, we investigate the impact of process variations on different types of c...
Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan,...
HPCA
2009
IEEE
14 years 10 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
DAC
2009
ACM
14 years 10 months ago
Statistical reliability analysis under process variation and aging effects
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan...
TC
2011
13 years 4 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...