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» Process Variations and their Impact on Circuit Operation
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ICCAD
2007
IEEE
131views Hardware» more  ICCAD 2007»
14 years 4 months ago
Low-overhead design technique for calibration of maximum frequency at multiple operating points
— Determination of maximum operating frequencies (Fmax) during manufacturing test at different operating voltages is required to: (a) to ensure that, for a Dynamic Voltage and Fr...
Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid...
ESSCIRC
2011
93views more  ESSCIRC 2011»
12 years 7 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...
DATE
2008
IEEE
119views Hardware» more  DATE 2008»
14 years 1 months ago
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
Drew C. Ness, David J. Lilja
TVLSI
2008
126views more  TVLSI 2008»
13 years 7 months ago
Body Bias Voltage Computations for Process and Temperature Compensation
With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. T...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
ASPDAC
2007
ACM
144views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method
With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a nu...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...