Sciweavers

63 search results - page 8 / 13
» Process variation robust clock tree routing
Sort
View
ISQED
2005
IEEE
162views Hardware» more  ISQED 2005»
14 years 1 months ago
Controlled-Load Limited Switch Dynamic Logic Circuit
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Now...
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 4 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
PATMOS
2007
Springer
14 years 1 months ago
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...
Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jia...
CVPR
2008
IEEE
14 years 2 months ago
Action recognition with motion-appearance vocabulary forest
In this paper we propose an approach for action recognition based on a vocabulary forest of local motionappearance features. Large numbers of features with associated motion vecto...
Krystian Mikolajczyk, Hirofumi Uemura
IROS
2007
IEEE
254views Robotics» more  IROS 2007»
14 years 1 months ago
3D datasets segmentation based on local attribute variation
— We present a Graph-based method for low-level segmentation of unfiltered 3D data. The core of this approach is based on the construction of a local neighborhood structure and ...
Carla Silva Rocha Aguiar, Sébastien Druon, ...