40 search results - page 3 / 8 » Process variation tolerant low power DCT architecture |
ISCA
2007
IEEE
14 years 4 months ago
2007
IEEE
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
DAC
2007
ACM
14 years 10 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
We present the implementation and analysis of a variation tolerant version of a switch-to-switch link in a NoC. The goal is to tolerate the effects of process variations on NoC ar...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) tec...