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ISCAS
2008
IEEE
141views Hardware» more  ISCAS 2008»
14 years 3 months ago
ASPA: Focal Plane digital processor array with asynchronous processing capabilities
— In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits fr...
Alexey Lopich, Piotr Dudek
SIGADA
1998
Springer
14 years 1 months ago
Algorithm Animation with Symbol Processing Robots
This experience report demonstrates several running programs with visual, animated, colorful displays of "algorithms in action." A common element of all of the programs ...
Brad S. Crawford
VTC
2010
IEEE
109views Communications» more  VTC 2010»
13 years 7 months ago
Joint and Distributed Linear Precoding for Centralised and Decentralised Multicell Processing
— Linear precoding techniques are designed for both joint and distributed Multi-Cell Processing (MCP), where both centralised and decentralised Channel State Information (CSI) ex...
Rong Zhang, Lajos Hanzo
ICCD
2004
IEEE
97views Hardware» more  ICCD 2004»
14 years 5 months ago
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...
John Lach, Jason Brandon, Kevin Skadron
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 2 months ago
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration
attributed to the high regularity of memories, PAs and FPGAs, and the ease with which they can be tested and reconfigured to avoid faulty elements. Digital microfluidicsbased bioch...
Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula