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» Processor Architectures for Ontogenesis
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ICS
2007
Tsinghua U.
15 years 10 months ago
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
Jung Ho Ahn, Mattan Erez, William J. Dally
IEEEPACT
2006
IEEE
15 years 10 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
SAC
2005
ACM
15 years 10 months ago
Motion estimation performance of the TM3270 processor
Motion estimation constitutes a significant computational part of video standards such as MPEG2, MPEG4, and H264/AVC. This paper evaluates the performance of a motion estimation a...
Jan-Willem van de Waerdt, Gerrit A. Slavenburg, Je...
EMSOFT
2004
Springer
15 years 9 months ago
Towards direct execution of esterel programs on reactive processors
Esterel is a system-level language for the modelling, verification and synthesis of control dominated (reactive) embedded systems. Existing Esterel compilers generate intermediat...
Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Day...
CASES
2003
ACM
15 years 9 months ago
Programming challenges in network processor deployment
Programming multi-processor ASIPs, such as network processors, remains an art due to the wide variety of architectures and due to little support for exploring different implement...
Chidamber Kulkarni, Matthias Gries, Christian Saue...