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» Processor Architectures for Ontogenesis
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RTAS
2005
IEEE
15 years 10 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
15 years 10 months ago
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design method...
Masanori Hariyama, Michitaka Kameyama, Yasuhiro Ko...
RTAS
2008
IEEE
15 years 10 months ago
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
Sibin Mohan, Frank Mueller
LCTRTS
2007
Springer
15 years 10 months ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
IPPS
1998
IEEE
15 years 8 months ago
A Clustered Approach to Multithreaded Processors
With aggressive superscalar processors delivering diminishing returns, alternate designs that make good use of the increasing chip densities are actively being explored. One such ...
Venkata Krishnan, Josep Torrellas