This paper presents a new technique for global energy optimization through coordinated functional partitioning and speed selection for embedded processors interconnected by a high...
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intende...
Abstract. As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. Th...
— On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...