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MICRO
2010
IEEE
115views Hardware» more  MICRO 2010»
15 years 2 months ago
Per-Thread Cycle Accounting
This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been execu...
Stijn Eyerman, Lieven Eeckhout
SAMOS
2010
Springer
15 years 2 months ago
Interleaving granularity on high bandwidth memory architecture for CMPs
—Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip m...
Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex...
MICRO
2007
IEEE
141views Hardware» more  MICRO 2007»
15 years 10 months ago
Composable Lightweight Processors
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
Changkyu Kim, Simha Sethumadhavan, M. S. Govindan,...
ISPASS
2008
IEEE
15 years 10 months ago
Metrics for Architecture-Level Lifetime Reliability Analysis
Abstract— This work concerns metrics for evaluating microarchitectural enhancements to improve processor lifetime reliability. A commonly reported reliability metric is mean time...
Pradeep Ramachandran, Sarita V. Adve, Pradip Bose,...
ICPP
2008
IEEE
15 years 10 months ago
XMT-GPU: A PRAM Architecture for Graphics Computation
The shading processors in graphics hardware are becoming increasingly general-purpose. We test, through simulation and benchmarking, the potential performance impact of replacing ...
Thomas M. DuBois, Bryant Lee, Yi Wang, Marc Olano,...