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ICPP
2009
IEEE
15 years 1 months ago
A Resource Optimized Remote-Memory-Access Architecture for Low-latency Communication
This paper introduces a new highly optimized architecture for remote memory access (RMA). RMA, using put and get operations, is a one-sided communication function which amongst ot...
Mondrian Nüssle, Martin Scherer, Ulrich Br&uu...
SAMOS
2007
Springer
15 years 10 months ago
Evaluating Large System-on-Chip on Multi-FPGA Platform
This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on...
Ari Kulmala, Erno Salminen, Timo D. Hämä...
JILP
2000
79views more  JILP 2000»
15 years 3 months ago
A Comparative Survey of Load Speculation Architectures
Load latency remains a signi cant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Predi...
Brad Calder, Glenn Reinman
TPDS
2010
144views more  TPDS 2010»
15 years 2 months ago
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
David A. Zier, Ben Lee
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
15 years 1 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...