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» Processor Architectures for Ontogenesis
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117
Voted
ISCC
2006
IEEE
123views Communications» more  ISCC 2006»
15 years 10 months ago
WISENEP: A Network Processor for Wireless Sensor Networks
Abstract— Wireless sensor networks are ad hoc networks comprised mainly of small sensor nodes with limited resources and one or more base stations, which are much more powerful l...
Andre Mota, Leonardo B. Oliveira, Felipe F. Rocha,...
139
Voted
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 9 months ago
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
Prabhat Mishra, Nikil D. Dutt
SAC
2005
ACM
15 years 9 months ago
A code compression advisory tool for embedded processors
We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-ti...
Sreejith K. Menon, Priti Shankar
122
Voted
APCSAC
2004
IEEE
15 years 7 months ago
Dynamic Reallocation of Functional Units in Superscalar Processors
In the context of general-purpose processing, an increasing number of diverse functional units are added to cover a wide spectrum of applications. However, it is still possible to ...
Marc Epalza, Paolo Ienne, Daniel Mlynek
IEEECIT
2010
IEEE
15 years 2 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...