Functional Coverage Driven Test Generation for Validation of Pipelined Processors

Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validation of such systems is the lack of a suitable functional coverage metric. This paper presents a functional coverage based test generation technique for pipelined architectures. The proposed methodology makes three important contributions. First, a general graphtheoretic model is developed that can capture the structure and behavior (instruction-set) of a wide variety of pipelined processors. Second, we propose a functional fault model that is used to define the functional coverage for pipelined architectures. Finally, test generation procedures are presented that accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. Our experimental results on two pipelined processor models demonstrate that the number of test programs generated by...

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Prabhat Mishra, Nikil D. Dutt
• Keywords: DATE 2005, Functional Coverage, Functional Fault Model, Hardware, Test Generation