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» Processor Architectures for Ontogenesis
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TC
2010
15 years 2 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
ASPLOS
2012
ACM
13 years 12 months ago
DreamWeaver: architectural support for deep sleep
Numerous data center services exhibit low average utilization leading to poor energy efficiency. Although CPU voltage and frequency scaling historically has been an effective mea...
David Meisner, Thomas F. Wenisch
ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
16 years 1 months ago
Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. In this paper, a distributed re...
Santithorn Bunchua, D. Scott Wills, Linda M. Wills
ISCA
2007
IEEE
128views Hardware» more  ISCA 2007»
15 years 10 months ago
Performance and security lessons learned from virtualizing the alpha processor
Virtualization has become much more important throughout the computer industry both to improve security and to support multiple workloads on the same hardware with effective isola...
Paul A. Karger
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
15 years 10 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll