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» Processor Modeling for Hardware Software Codesign
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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 11 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
HPCA
1996
IEEE
13 years 11 months ago
Improving Release-Consistent Shared Virtual Memory Using Automatic Update
Shared virtual memory is a software technique to provide shared memory on a network of computers without special hardware support. Although several relaxed consistency models and ...
Liviu Iftode, Cezary Dubnicki, Edward W. Felten, K...
ISCA
2010
IEEE
239views Hardware» more  ISCA 2010»
13 years 11 months ago
Sentry: light-weight auxiliary memory access control
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...
Arrvindh Shriraman, Sandhya Dwarkadas
INFORMS
1998
142views more  INFORMS 1998»
13 years 6 months ago
Distributed State Space Generation of Discrete-State Stochastic Models
High-level formalisms such as stochastic Petri nets can be used to model complex systems. Analysis of logical and numerical properties of these models often requires the generatio...
Gianfranco Ciardo, Joshua Gluckman, David M. Nicol
IPPS
2007
IEEE
14 years 1 months ago
Invited Paper: A Compile-time Cost Model for OpenMP
OpenMP has gained wide popularity as an API for parallel programming on shared memory and distributed shared memory platforms. It is also a promising candidate to exploit the emer...
Chunhua Liao, Barbara M. Chapman