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    ICCD
    1996
    IEEE
    145views Hardware» more  ICCD 1996»
    Can Trace-Driven Simulators Accurately Predict Superscalar Performance?
    13 years 11 months ago
    Can Trace-Driven Simulators Accurately Predict Superscalar Performance?
    Download  www.ece.wisc.edu
    There are four crucial issues associated with performance simulators: simulator retargetability, simulator validation, simulation speed and simulation accuracy. This paper documen...
    Bryan Black, Andrew S. Huang, Mikko H. Lipasti, Jo...
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    ASPDAC
    2000
    ACM
    95views Hardware» more  ASPDAC 2000»
    Retargetable estimation scheme for DSP architecture selection
    13 years 11 months ago
    Retargetable estimation scheme for DSP architecture selection
    Download  bwrc.eecs.berkeley.edu
    — Given the recent wave of innovation and diversification in digital signal processor (DSP) architecture, the need for quickly evaluating the true potential of considered archite...
    Naji Ghazal, A. Richard Newton, Jan M. Rabaey
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    PLDI
    2006
    ACM
    92views Programming Languages» more  PLDI 2006»
    Automatic instruction scheduler retargeting by reverse-engineering
    14 years 1 months ago
    Automatic instruction scheduler retargeting by reverse-engineering
    Download  liberty.princeton.edu
    In order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a ...
    Matthew J. Bridges, Neil Vachharajani, Guilherme O...
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    DAC
    1996
    ACM
    121views Computer Architecture» more  DAC 1996»
    Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures
    13 years 11 months ago
    Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures
    Download  www.cs.york.ac.uk
    The advent of parallel executing Address Calculation Units (ACUs) in Digital Signal Processor (DSP) and Application Specific InstructionSet Processor (ASIP) architectures has made...
    Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerra...
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    CODES
    2006
    IEEE
    158views Software Engineering» more  CODES 2006»
    A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
    14 years 1 months ago
    A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
    Download  people.bu.edu
    Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
    Wei Qin, Joseph D'Errico, Xinping Zhu
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