151 search results - page 23 / 31 » Processor Verification with hwBugHunt |
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
ISCA
2011
IEEE
13 years 2 months ago
2011
IEEE
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
DAC
2008
ACM
14 years 12 months ago
2008
ACM
Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverag...
POPL
2009
ACM
14 years 11 months ago
2009
ACM
Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, t...
POPL
2010
ACM
14 years 8 months ago
2010
ACM
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...