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TVLSI
2002
130views more  TVLSI 2002»
13 years 10 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
BIRTHDAY
2006
Springer
14 years 2 months ago
Realistic Worst-Case Execution Time Analysis in the Context of Pervasive System Verification
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
Steffen Knapp, Wolfgang J. Paul
JSW
2007
126views more  JSW 2007»
13 years 10 months ago
Supporting UML Sequence Diagrams with a Processor Net Approach
— UML sequence diagrams focus on the interaction between different classes. For distributed real time transaction processing it is possible to end up with complex sequence diagra...
Tony Spiteri Staines
ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
14 years 22 days ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
TC
1998
13 years 10 months ago
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
Fong Pong, Michael C. Browne, Gunes Aybay, Andreas...