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GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
13 years 8 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
CN
2006
87views more  CN 2006»
13 years 8 months ago
Lightweight thread tunnelling in network applications
Abstract. Active Network nodes are increasingly being used for nontrivial processing of data streams. These complex network applications typically benefit from protection between t...
Austin Donnelly
NOCS
2009
IEEE
14 years 2 months ago
Silicon-photonic clos networks for global on-chip communication
Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, h...
Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Sco...
FCCM
2004
IEEE
101views VLSI» more  FCCM 2004»
13 years 11 months ago
Secure Remote Control of Field-programmable Network Devices
A circuit and an associated lightweight protocol have been developed to secure communication between a control console and remote programmable network devices1 . The circuit provi...
Haoyu Song, Jing Lu, John W. Lockwood, James Mosco...
ERSA
2006
111views Hardware» more  ERSA 2006»
13 years 9 months ago
Promises and Pitfalls of Reconfigurable Supercomputing
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
Maya Gokhale, Christopher Rickett, Justin L. Tripp...