852 search results - page 88 / 171 » Programmable Packet Scheduling |
135
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PDP
2008
IEEE
15 years 8 months ago
2008
IEEE
This paper examines the scalable parallel implementation of QR factorization of a general matrix, targeting SMP and multi-core architectures. Two implementations of algorithms-by-...
102
Voted
EUROPDS
1997
15 years 3 months ago
1997
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
102
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DATE
2005
IEEE
15 years 7 months ago
2005
IEEE
In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main proces...
131
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DATE
2010
IEEE
15 years 7 months ago
2010
IEEE
— Ubiquitous image processing tasks (such as transform decompositions, filtering and motion estimation) do not currently provide graceful degradation when their clock-cycles budg...
119
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FPL
2009
Springer
15 years 6 months ago
2009
Springer
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...