Sciweavers

304 search results - page 6 / 61
» Programmable memory blocks supporting content-addressable me...
Sort
View
WOMPAT
2001
Springer
13 years 12 months ago
CableS : Thread Control and Memory System Extensions for Shared Virtual Memory Clusters
Clusters of high-end workstations and PCs are currently used in many application domains to perform large-scale computations or as scalable servers for I/O bound tasks. Although cl...
Peter Jamieson, Angelos Bilas
ASPLOS
2006
ACM
14 years 1 months ago
Unbounded page-based transactional memory
Exploiting thread level parallelism is paramount in the multi-core era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded progra...
Weihaw Chuang, Satish Narayanasamy, Ganesh Venkate...
DATE
2010
IEEE
130views Hardware» more  DATE 2010»
13 years 11 months ago
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller
Abstract—Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We p...
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming C...
SBACPAD
2003
IEEE
137views Hardware» more  SBACPAD 2003»
14 years 22 days ago
Exploring Memory Hierarchy with ArchC
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
IPPS
2008
IEEE
14 years 1 months ago
Intermediate checkpointing with conflicting access prediction in transactional memory systems
Transactional memory systems promise to reduce the burden of exposing thread-level parallelism in programs by relieving programmers from analyzing complex inter-thread dependences...
M. M. Waliullah, Per Stenström