Abstract. We present a strategy to develop, in a functional setting, correct, e cient and portable Divide-and-Conquer (DC) programs for massively parallel architectures. Starting f...
The paper presents the implementation of a railway control system, as a means of assessing the potential of coordination languages to be used for modelling software architectures f...
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
Recently, a mathematical proof is obtained in (Liu, Chiu, Xu, 2004) on the so called one-bit-matching conjecture that all the sources can be separated as long as there is an one-to...
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar