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CGO
2005
IEEE
14 years 1 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 2 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
SECON
2010
IEEE
13 years 5 months ago
QoI-Aware Wireless Sensor Network Management for Dynamic Multi-Task Operations
Abstract--This paper considers the novel area of quality-ofinformation (QoI)-aware network management of multitasking wireless sensor networks (WSNs). Specifically, it provides an ...
Chi Harold Liu, Chatschik Bisdikian, Joel W. Branc...
ACMMSP
2005
ACM
99views Hardware» more  ACMMSP 2005»
14 years 28 days ago
Gated memory control for memory monitoring, leak detection and garbage collection
ct In the past, program monitoring often operates at the code level, performing checks at function and loop boundaries. Recent research shows that profiling analysis can identify ...
Chen Ding, Chengliang Zhang, Xipeng Shen, Mitsunor...
PPOPP
2003
ACM
14 years 18 days ago
CC-MPI: a compiled communication capable MPI prototype for ethernet switched clusters
Compiled communication has recently been proposed to improve communication performance for clusters of workstations. The idea of compiled communication is to apply more aggressive...
Amit Karwande, Xin Yuan, David K. Lowenthal