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ISPASS
2009
IEEE
14 years 5 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
CCS
2009
ACM
14 years 5 months ago
Large-scale malware indexing using function-call graphs
A major challenge of the anti-virus (AV) industry is how to effectively process the huge influx of malware samples they receive every day. One possible solution to this problem i...
Xin Hu, Tzi-cker Chiueh, Kang G. Shin
FCCM
2009
IEEE
148views VLSI» more  FCCM 2009»
14 years 5 months ago
A Packet Generator on the NetFPGA Platform
— A packet generator and network traffic capture system has been implemented on the NetFPGA. The NetFPGA is an open networking platform accelerator that enables rapid developmen...
G. Adam Covington, Glen Gibb, John W. Lockwood, Ni...
ICSEA
2009
IEEE
14 years 5 months ago
Ontology Driven E-Government
: This paper presents an approach to model ontologies for the e-Government domain as a basis for an integrated e-Government environment. Over the last couple of years the applicati...
Peter Salhofer, Bernd Stadlhofer, Gerald Tretter
CGO
2008
IEEE
14 years 5 months ago
Cole: compiler optimization level exploration
Modern compilers implement a large number of optimizations which all interact in complex ways, and which all have a different impact on code quality, compilation time, code size,...
Kenneth Hoste, Lieven Eeckhout