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ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
14 years 3 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
PODC
2003
ACM
14 years 3 months ago
Geometric ad-hoc routing: of theory and practice
All too often a seemingly insurmountable divide between theory and practice can be witnessed. In this paper we try to contribute to narrowing this gap in the field of ad-hoc rout...
Fabian Kuhn, Roger Wattenhofer, Yan Zhang, Aaron Z...
SIGSOFT
2003
ACM
14 years 3 months ago
Refinements and multi-dimensional separation of concerns
1 Step-wise refinement (SWR) asserts that complex programs can be derived from simple programs by progressively adding features. The length of a program specification is the number...
Don S. Batory, Jia Liu, Jacob Neal Sarvela
PLDI
2010
ACM
14 years 2 months ago
Adversarial memory for detecting destructive races
Multithreaded programs are notoriously prone to race conditions, a problem exacerbated by the widespread adoption of multi-core processors with complex memory models and cache coh...
Cormac Flanagan, Stephen N. Freund
DSN
2002
IEEE
14 years 2 months ago
Model Checking Performability Properties
Model checking has been introduced as an automated technique to verify whether functional properties, expressed in a formal logic like computational tree logic (CTL), do hold in a...
Boudewijn R. Haverkort, Lucia Cloth, Holger Herman...