2057 search results - page 380 / 412 » Quadratic placement using an improved timing model |
151
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ICCAD
2004
IEEE
16 years 2 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
174
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CVPR
2009
IEEE
16 years 22 days ago
2009
IEEE
Recent years have seen the development of fast and accurate algorithms for detecting objects in images. However, as the size of the scene grows, so do the running-times of these a...
223
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SPAA
1993
ACM
15 years 10 months ago
1993
ACM
d Abstract) Thomas H. Cormen Leonard F. Wisniewski Department of Mathematics and Computer Science Dartmouth College We give asymptotically equal lower and upper bounds for the num...
166
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TC
1998
15 years 5 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
165
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PPOPP
2010
ACM
16 years 3 months ago
2010
ACM
Many large-scale parallel programs follow a bulk synchronous parallel (BSP) structure with distinct computation and communication phases. Although the communication phase in such ...