DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs

In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chip performance constraint. This is a well-studied topic and a very difficult task (NP-hard). The contributions of this paper are as follows: (i) we consider the potential node duplications during the cut enumeration/generation procedure so the mapping costs encoded in the cuts drive the area-optimization objective more effectively; (ii) after the timing constraint is determined, we will relax the non-critical paths by searching the solution space considering both local and global optimality information to minimize mapping area; (iii) an iterative cut selection procedure is carried out that further explores and perturbs the solution space to improve solution quality. We guarantee optimal mapping depth under the unit delay model. Experimental results show that our mapping algorithm, named DAOmap, produces signif...

• Type: Conference
• Year: 2004
• Where: ICCAD
• Authors: Deming Chen, Jason Cong
• Keywords: Hardware, ICCAD 2004, Minimization Mapping Algorithm, Optimal Mapping Depth, Technology Mapping Problem