352 search results - page 10 / 71 » Quantifying Instruction Criticality |
AAAI
1994
13 years 8 months ago
1994
CAT0 is an instructions environment for practicing basic skills of legal research: to use cases in arguments about a problem situation and to test a theory about a legal domain. U...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
—L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough t...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
LCTRTS
1998
Springer
13 years 11 months ago
1998
Springer
Instruction scheduling is a necessary step in compiling for many modern microprocessors. Traditionally, global instruction scheduling techniques have outperformed local techniques....