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ISPASS
2005
IEEE
14 years 4 months ago
Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection
Simulation-based microarchitecture research is often hindered by the slow speed of simulators. In this work, we propose a novel statistical technique to identify highly representa...
Ram Srinivasan, Jeanine Cook, Shaun Cooper
MICRO
2003
IEEE
96views Hardware» more  MICRO 2003»
14 years 4 months ago
Using Interaction Costs for Microarchitectural Bottleneck Analysis
Attacking bottlenecks in modern processors is difficult because many microarchitectural events overlap with each other. This parallelism makes it difficult to both (a) assign a ...
Brian A. Fields, Rastislav Bodík, Mark D. H...
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
14 years 4 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
CCS
2006
ACM
14 years 2 months ago
Puppetnets: misusing web browsers as a distributed attack infrastructure
Most of the recent work on Web security focuses on preventing attacks that directly harm the browser's host machine and user. In this paper we attempt to quantify the threat ...
V. T. Lam, Spyros Antonatos, Periklis Akritidis, K...
CC
2009
Springer
153views System Software» more  CC 2009»
14 years 11 months ago
Register Spilling and Live-Range Splitting for SSA-Form Programs
Register allocation decides which parts of a variable's live range are held in registers and which in memory. The compiler inserts spill code to move the values of variables b...
Matthias Braun, Sebastian Hack