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» Quantifying Instruction Criticality
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HPCA
2007
IEEE
14 years 7 months ago
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
Kiran Puttaswamy, Gabriel H. Loh
LCTRTS
2009
Springer
14 years 2 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava
PIMRC
2008
IEEE
14 years 1 months ago
Active Highways (Position Paper)
—Highways are an essential component of our society because they are critical to quality of life and to local and national economies. Under good conditions, highways provide a sa...
Liviu Iftode, Stephen Smaldone, Mario Gerla, James...
SBACPAD
2008
IEEE
100views Hardware» more  SBACPAD 2008»
14 years 1 months ago
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
Jesús Alastruey, Teresa Monreal, Francisco ...
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
14 years 1 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang