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DAC
2001
ACM
14 years 9 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
VTC
2008
IEEE
165views Communications» more  VTC 2008»
14 years 3 months ago
Operation and Performance of Vehicular Ad-Hoc Routing Protocols in Realistic Environments
—Vehicle-to-vehicle and vehicle-to-infrastructure wireless communications are currently under development to improve traffic efficiency and safety. Routing protocols enabling mul...
Ramon Bauza, Javier Gozálvez, Miguel Sepulc...
VTC
2008
IEEE
159views Communications» more  VTC 2008»
14 years 3 months ago
Binary Demodulation in Rayleigh Fading with Noisy Channel Estimates - Detector Structures and Performance
Abstract— In previous work, we studied the structure and performance of optimum maximum-likelihood receivers for binary antipodal and orthogonal signals in the presence of Gaussi...
Amir Ali Basri, Teng Joon Lim
INFOCOM
2006
IEEE
14 years 2 months ago
Overhead and Performance Study of the General Internet Signaling Transport (GIST) Protocol
— The General Internet Signaling Transport (GIST) protocol is currently being developed as the base protocol component in the IETF Next Steps In Signaling (NSIS) protocol stack t...
Xiaoming Fu, Henning Schulzrinne, Hannes Tschofeni...
FPL
2000
Springer
116views Hardware» more  FPL 2000»
14 years 12 days ago
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
Abstract. Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercia...
Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard ...