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» Quantifying the cost of context switch
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ISCA
2012
IEEE
280views Hardware» more  ISCA 2012»
12 years 2 days ago
A case for random shortcut topologies for HPC interconnects
—As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance C...
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Ama...
IPPS
1999
IEEE
14 years 1 months ago
Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
Jan Jonsson, Henrik Lönn, Kang G. Shin
AIPS
2006
13 years 11 months ago
Structure and Problem Hardness: Goal Asymmetry and DPLL Proofs in SAT-Based Planning
In AI Planning, as well as Verification, a successful method is to compile the application into boolean satisfiability (SAT), and solve it with state-of-the-art DPLL-based procedu...
Jörg Hoffmann, Carla P. Gomes, Bart Selman
ADBIS
2006
Springer
93views Database» more  ADBIS 2006»
14 years 3 months ago
An On-Line Reorganization Framework for SAN File Systems
While the cost per megabyte of magnetic disk storage is economical, organizations are alarmed by the increasing cost of managing storage. Storage Area Network (SAN) architectures ...
Shahram Ghandeharizadeh, Shan Gao, Chris Gahagan, ...
HPCA
2003
IEEE
14 years 10 months ago
Mini-Threads: Increasing TLP on Small-Scale SMT Processors
Several manufacturers have recently announced the first simultaneous-multithreaded processors, both as single CPUs and as components of multi-CPU chips. All are small scale, compr...
Joshua Redstone, Susan J. Eggers, Henry M. Levy