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ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
14 years 9 hour ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
FOSSACS
2009
Springer
14 years 2 months ago
Facets of Synthesis: Revisiting Church's Problem
In this essay we discuss the origin, central results, and some perspectives of algorithmic synthesis of nonterminating reactive programs. We recall the fundamental questions raised...
Wolfgang Thomas
IISWC
2008
IEEE
14 years 2 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
TCAD
2010
121views more  TCAD 2010»
13 years 2 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
EUROPAR
2006
Springer
13 years 11 months ago
Toward a Definition of and Linguistic Support for Partial Quiescence
Abstract. The global quiescence of a distributed computation (or distributed termination detection) is an important problem. Some concurrent programming languages and systems provi...
Billy Yan-Kit Man, Hiu Ning (Angela) Chan, Andrew ...