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ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
14 years 2 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
ANCS
2005
ACM
14 years 2 months ago
Segmented hash: an efficient hash table implementation for high performance networking subsystems
Hash tables provide efficient table implementations, achieving O(1), query, insert and delete operations at low loads. However, at moderate or high loads collisions are quite freq...
Sailesh Kumar, Patrick Crowley
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
14 years 1 months ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi
CONEXT
2009
ACM
13 years 9 months ago
BUFFALO: bloom filter forwarding architecture for large organizations
In enterprise and data center networks, the scalability of the data plane becomes increasingly challenging as forwarding tables and link speeds grow. Simply building switches with...
Minlan Yu, Alex Fabrikant, Jennifer Rexford
DSN
2005
IEEE
14 years 2 months ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh