214 search results - page 22 / 43 » Quasi-Resonant Interconnects: A Low Power Design Methodology |
TC
2008
13 years 7 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
A low power wireless intercom system is designed and implemented. Two fully-operational ASICs, integrating custom and commercial IP, implement the entire digital portion of the pr...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
DFT
2007
IEEE
14 years 2 months ago
2007
IEEE
The network-on-chip (NoC) paradigm is seen as a way of facilitating the integration of a large number of computational and storage blocks on a chip to meet several performance and...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...