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» Quasi-interpretation Synthesis by Decomposition
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DATE
2009
IEEE
120views Hardware» more  DATE 2009»
14 years 3 months ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, ...
DATE
2007
IEEE
146views Hardware» more  DATE 2007»
14 years 3 months ago
Data-flow transformations using Taylor expansion diagrams
Abstract: An original technique to transform functional representation of the design into a structural representation in form of a data flow graph (DFG) is described. A canonical,...
Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-P...
ICASSP
2010
IEEE
13 years 7 months ago
A hierarchical Bayesian model for frame representation
In many signal processing problems, it may be fruitful to represent the signal under study in a redundant linear decomposition called a frame. If a probabilistic approach is adopt...
Lotfi Chaâri, Jean-Christophe Pesquet, Jean-...
ASPDAC
2008
ACM
92views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Decomposition based approach for synthesis of multi-level threshold logic circuits
Scaling is currently the most popular technique used to improve performance metrics of CMOS circuits. This cannot go on forever because the properties that are responsible for the ...
Tejaswi Gowda, Sarma B. K. Vrudhula
ASYNC
2004
IEEE
98views Hardware» more  ASYNC 2004»
14 years 13 days ago
Synthesis of Speed Independent Circuits Based on Decomposition
This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesi...
Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers