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» Queue Management in Network Processors
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DSN
2008
IEEE
14 years 3 months ago
Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors
As semiconductor technology scales, reliability is becoming an increasingly crucial challenge in microprocessor design. The rSRAM and voltage scaling are two promising circuit-lev...
Xin Fu, Tao Li, José A. B. Fortes
INFOCOM
2005
IEEE
14 years 2 months ago
An analytic framework for modeling peer to peer networks
Abstract—This paper presents an analytic framework to evaluate the performance of peer to peer (P2P) networks. Using the time to download or replicate an arbitrary file as the m...
Krishna K. Ramachandran, Biplab Sikdar
IPPS
2006
IEEE
14 years 2 months ago
Compiler assisted dynamic management of registers for network processors
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
R. Collins, Fernando Alegre, Xiaotong Zhuang, Sant...
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
14 years 14 days ago
Mixed-clock issue queue design for energy aware, high-performance cores
- Globally-Asynchronous, Locally-Synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal ...
Venkata Syam P. Rapaka, Emil Talpes, Diana Marcule...
QOFIS
2000
Springer
14 years 9 days ago
Random Early Marking
In this paper we present an optimisation approach to congestion flow control. The initial context of this approach was as a rate based flow control in ATM networks. We describe te...
Sanjeewa Athuraliya, Steven H. Low, David E. Lapsl...