79 search results - page 5 / 16 » Queues, stores, and tableaux |
ISLPED
2003
ACM
14 years 3 months ago
2003
ACM
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
ISLPED
2006
ACM
14 years 3 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
ISCA
2012
IEEE
12 years 6 days ago
2012
IEEE
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
EUROPAR
2001
Springer
14 years 2 months ago
2001
Springer
We present randomized and deterministic algorithms for many-to-one routing on an n-node two-dimensional mesh under the store-and-forward model of packet routing. We consider the g...
IEEEARES
2006
IEEE
14 years 3 months ago
2006
IEEE
We present a novel approach for the implementation of efficient and dependable web service engines (WSEs). A WSE instance represents a single node in a distributed network of par...