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FPL
2010
Springer
129views Hardware» more  FPL 2010»
13 years 6 months ago
FPGA Implementations of the Round Two SHA-3 Candidates
Abstract--The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper present...
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilt...
TOG
2002
112views more  TOG 2002»
13 years 8 months ago
Ray tracing on programmable graphics hardware
Recently a breakthrough has occurred in graphics hardware: fixed function pipelines have been replaced with programmable vertex and fragment processors. In the near future, the gr...
Timothy J. Purcell, Ian Buck, William R. Mark, Pat...
PC
2011
318views Management» more  PC 2011»
13 years 3 months ago
High-performance message-passing over generic Ethernet hardware with Open-MX
In the last decade, cluster computing has become the most popular high-performance computing architecture. Although numerous technological innovations have been proposed to improv...
Brice Goglin
CISS
2011
IEEE
13 years 6 hour ago
Hardware accelerated visual attention algorithm
— We present a hardware-accelerated implementation of a bottom-up visual attention algorithm. This algorithm generates a multi-scale saliency map from differences in image intens...
Polina Akselrod, Faye Zhao, Ifigeneia Derekli, Cl&...
IMCSIT
2010
13 years 5 months ago
Software and hardware in the loop component for an IEC 61850 Co-Simulation platform
The deployment of IEC61850 standard in the world of substation automation system brings to the use of specific strategies for architecture testing. To validate IEC61850 architectur...
Haffar Mohamad, Thiriet Jean Marc